ECPi PLL
The ECPi PLL uses the RPI's pixel clock as a source, and generates both the FPGA's pixel clock and the FPGA's TMDS/DVI/HDMI clock phase aligned with the input, and compensated for the FPGA's clock distribution network.
Why does dividing increase the frequency??? For anyone who is not so good at digital electronics, the dividers are just counters. Count to 5 or 25 and change the output. The magic is all in how the analog PLL does the multiplication. It has to boost the output frequency and shift its phase until the divided and delayed feedback signal matches the input signal.
- Configuring the ECP5 PLL The best source of information on configuring the pll.
- EHXPLL Yosys black box definition of the module with both default parameters and I/O wires.
- ECP5 Clock Generation
- Lattice PLL Documentation
- Lattice ECP5 DataSheet
- PLL Multiplier Divider Calculator
- YOSYS EHXPLL default values.
- IcePi Zero PLL Source
- Project Trellis ULX3S Example
- Project Trellis SocVersa5G Example
- Project Trellis soc_ecp5_evn
- More thoughts and links
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