My goal was to find a low-end open-source FPGA for ECPi Camerawhich did everything I needed but no more. I do not like wasting resources. Ice40 is really cheap, but its functionality and speed are not competitive with a cheaper RaspberryPi RP2350 microcontroller. The Chinese Gowin is also cheap, but has multiple issues. GateMate is made in Europe, very innovative, but its high speed I/O is limited to a single lane 5G Serdes, and most of the important high speed protocols require either multiple lanes (MIPI CSI), very complex additional circuitry (USB-3) or excessively complex control logic (PCIe). There are larger more powerful open source chips, but they are also more expensive, or just not available until the AI bubble bursts and manufacturing capacity becomes available.
It is a 40nm process, at the low end of the market, but has a lot of great functionality.
Lattice ECP5 feels just right. It supports a wide range of digital I/O. Multiple voltages, high speed gearing, higher speed Serdes, 3.2G by default which is enough for 2.5G Ethernet. There are multiple shipping boards one can use to get started. There is a very active Radiona ULX3S open source community supporthing this chip. The more I learn about the chip, the more I like it.
The ECP5 family supports 1080p (1920 * 1080) DVI out at 60 frames per second. ICE40 and GateMate cannot do that. ECP5 supports SDRAM as video frame buffers at the same 1080p @60FPS rate. This involveds DDR3 at 800 Transactions/s. 3.3 V is supported which makes it easy to interface to the Raspberry Pi ecosystem. In contrast, GateMate and Lattice's NX17/33/40 need level shifters to connect to RPI chips. The SerDes interfaces support MIPI-DSI, Embedded Display Port, multiGigabit Ethernet, PCIe, and more. ECP5 supports LVDS with 7:1 gearing, which would work well with the Sony Block Camera with 30 x physical zoom.
Inside the ECP5 there are 12K to 85K LUT-4s, 576Kbits to 3.7Mbits BRAMS, and 28 to 156 18 × 18 multipliers. The full details can be read in the ECP5 Datasheet.
IcePi Zero. View
The IcePi Zero is an excellent example of an application specific FPGA circuit board.
Most FPGA boards are designed for general use . They do a little of everything, and do nothing that well. The icePi Zero was designed for retro computing. It does that and everything else is leaves to other boards in the large Raspberry Pi ecosystem.
The board designer wanted a board to run soft cpu cores. It has all that is needed for a soft core, the rest it leaves to the Raspberry Pi ecosystem. This makes for a small and inexpensive board. $64 = € 54 the same prices as the Olimex GateMate with 2 external RAMs, but Icepi has a lot more bang for the buck.
If you look at the circuitry, it is really quite beautiful. Somebody put a lot of energy into this product. And the board is open source, so if I need to I can make whatever changes I need, and produce a new board. I also very much like the FPGA he chose for this board.
It has DVI out, a fast SDRAM, two USB ports for the. keyboard and mouse, an SD card reader, and a USB port to connect to the desktop. Everything else it leaves to the Raspberry Pi ecosystem, which is easy to plug into since it has the Raspberry Pi form factor. Lattice ECP5 is an older chip, it still supports 3.3V peripherals, which is perfect for interfacing to the Raspberry Pi ecosystem: no level shifters are needed.
The designer scratched his own itch, and in the process perfectly targeted the market. There are not many trained FPGA developers, but there are a lot of software developers who want to become FPGA developers. Their first project is usually a soft CPU core. So they want a board like this. I did the same thing for my master's thesis in electrical engineering. In the process I learned that soft cores on FPGAs are so much slower than dedicated chips. For the FPGA to be competitive, it needs a much more parallel application, which is why I moved to video. processing.
While the high level design is perfect, I worry was that there will be bugs in this board. This is the first board the designer built. Since it is an open source board, a lot of experts gave him advice, but still mistakes could have been made. And indeed that happened. The first batch of boards were received on December 17th, 2025, two of the pins were reversed, and on Jan 1 2026 version 1.3 of the board was released. So if you are doing mainstream soft cpu cores you should now be fine, but for people like me who are doing something non mainstream, there is still a worry that there will be problems with the details.
Because this board is so small and simple, it is easy to modify it. There is already a pull request for a variant with an Analog. to Digital Converter (ADC).
I really like that the IcePi Zero was designed for a specific application: retro computing.
ULX3S. View
ULX3S has a great reputation. Since it was released in 2016, a huge IP ecosystem has developed.
It is for the educational market. It has many permipherals, and comes in three different sizes. When I first started studying FPGAS in 2022 it was the board that everyone recommended. It is still a great choice, although there are now less expensive options albeit with fewer peripherals.
Here is a page of ULX3S Links.
ULX4M. View
ULX4M has a Lattice ECP5 with Flash, RAM and ethernet which can plug into Raspberry Pi compute module 4 compatible base boards.
There are two versions of the ULX4M. The low cost ULX4M-LS will have SDRAM and a small FPGA. The high performance, more expensive, ULX4M-LD will have DDR3, 85K LUTs and 3.2Gps SerDes. To maximize memory bandwidth on the high performance ULX4M-LD SOM, the FPGA and high speed DDR3 SDRAM are on an expensive 6 layer circuit board.
The idea is to split the circuit board into two parts, the FPGA with memory, and a mass-produced base board. The base boards can be a Raspberry Pi 4 compute module base board such as the TOFU, or you can build an application specific base board for your needs. The initial base board reproduced the functionality of the ULX3S.
Multiple protocols including DisplayPort, multi Gbps Ethernet, PCIe, and MIPI can be supported by the four SerDes on the LD board. SerDes stands for SERializer DESerializer. SerDes takes a low speed parallel signal and serializes it into a single high speed differential pair running at up to 3.2 Gigabits per second (Gbps). That reduces the number of wires required. On Lattice ECP5, without overclocking, the internal signals are limited to 400 Mhz. Reportely with overclocking, the SerDes can reach 5Gbps on many chips. The ratio of the two speeds is called the gearing.
The differential signal has lower voltage swings then regular single ended signals. Power is proportional to the voltage swing squared, so it consumes a lot less power. It can run across twisted pairs or coaxial cable for longer distances than single ended signals. SerDes is less sensitive to noise, and generates less noise.
Low cost LS Variant
Lattice ECP5 LFE5U-12F-6BG381C
Ethernet 100Mbps: LAN8720A
32 MB SDRAM: IS42S16160G-7BL ( I could not find the link)
High Performance LD Variant
Lattice ECP5 LFE5U-85F-6BG381C Comes in multiple versions: 12, 25, 45 or 85K LUTs.
512MB DDR3: MT41K256M16TW-107
Ethernet 1Gbps: KSZ9031RNXCA
Both boards have the same FLASH chip:
W25Q128JVSIM NOR Flash spiFlash, 3V, 128M-bit, 4Kb Uniform Sector
MIPI D-PHY Bandwidth Matrix and Implementation. View
Documentation about MIPI D-Phy interface on ECP5.
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