ECPi Clocks

In order for the ECP5 and the RPI0 to work together their pixel clocks needs to be synchronized and in phase. If the pixel clocks are slightly different frequencies, they will drift apart and the HDMI timing requirements will be violated. There will be too much or too little data provided. The image will scroll and wrap. If the signals are out of phase, the setup and hold times will be violated leading to metastability. To deal with the phase problem, one could do Clock Domain Crossing (CDC) with Fifo queues, but I suspect that it is easier to just align the clocks on both chips using the FPGA's phase adjustment circuitry.

There are two relevant clocks: the oscillator and the pixel clock. The RPI0 19.2(?) Mhz oscillator can be published on dedicated clock ports. Ideally, it should be input into the dedicated FPGA clock input ports from which it is fed directly to the PLL. It can also be routed through the FPGA fabric, but the quality degrades. Since the IcePi Zero does not hardwire the PLL clock input port to the RPI0 clock output port, we will be sending the signal through the fabric.

Once the two chips share an osciallator signal, we need to synchronize their PLLs. PLL's work by first multiplying the frequency and then dividing it. The RPI0 Pixel clock is generated by first multiplying the oscillator frequency by a fractional number up to many GigaHz, and then dividing it. The ECP5 PLL is more limited than the RPI PLL. The FPGA PLL also multiplies the oscillator frequency by a number but only by integers from 1 to 128. The resulting signal should not exceed 800 Mhz. That signal is then divided by a number between 1 and 128. To keep the two pixel clocks synchronised, we need to use the same multiply and divide frequencies. The resulting Pixel clock frequency should then be as close as possible to the number specified by the VESA display standards.

The RPI0 OS calculates the PLL multiply and divide numbers based on available information. Setting FPGA compatible values may require hacks to the RPI0 Linux Kernel. The ULX3S ECP5 VHDL DVI RTL also provides some hacks if the default PLL values do not work.

The ECP5's PLL does include phase adjustment circuitry, so its pixel clock can be in phase with the RPI0's output pixel clock.

There is also an issue that it may not be possible to both publish RPI0 RGB788 and the oscillator signal at the same time . The documentation warns about this,focusing on the PWM. and SPI signals. Some testing and more reading will be required.

The first project will be to connect a RPI0 to an oscilliscope and see if the data is available. Can anyone recommend a USB 3 oscilliscope? Maybe time to join hackerspace Krakow.

Over time, I expect that this page will be expanded with more details. Particularly with the different screen resolutions. and their required PLL settings. As I read lots of different documents, useful bits and pieces will be found and added to this page.