Lattice FPGAs

Lattice ICE 40.    View      

Lattice ICE 40 was the initial FPGA supported by the open source Yosys synthesis suite.

ICE 40 is an older slower smaller and less expensive family of FPGAs. Great for educational projects, and simple applications. They are limited to 8K LUTs, and 100 Mhz. Most have small memories, the UP5K also has 1 Mbit of Large RAMs, but they are single port memories, and limited to 50Mhz.

The Pico-Ice and Pico2-Ice are recommended for beginners. Both use the wondrerful Pico Ice SDK. The Upduino 3.1 fixed the bugs of the previous versions, but retained the internal, less accurate oscilator as the default. And only 1 of 4 pins of the FTDI FT232H USB bridge are connected to the FPGA. At least they can be manually connected.

There are many open source circuit boards using Lattice FPGAs, but sadly most are not shipping.

Lattice CrossLink NX.    View      

These include MIPI CSI and DSI hard cores at 10 Gbps.

Lattice Nexus 17 33 and 40 add two 10Gbit/s MIPI CSI or DSI hard cores and large Block RAMs to the Lattice ECP 5 family. But they loose the Serdes abilities. NX 17 and 40 are supported by the open source Yosys platform, but NX 33 is not. It uses a different fabric, from a different Lattice family, and. adds USB-3 capabilities. Sadly as of June 2026, these are all back ordered for 2 years. But you can still buy the evaluation boards. They are a bit harder to use, needing a 12 power supply.

Lattice ECP5.    View      

Lattice ECP5 is currently my favorite FPGA.

My goal was to find a low-end open-source FPGA for ECPi Camerawhich did everything I needed but no more. I do not like wasting resources. Ice40 is really cheap, but its functionality and speed are not competitive with a cheaper RaspberryPi RP2350 microcontroller. The Chinese Gowin is also cheap, but has multiple issues. GateMate is made in Europe, very innovative, but its high speed I/O is limited to a single lane 5G Serdes, and most of the important high speed protocols require either multiple lanes (MIPI CSI), very complex additional circuitry (USB-3) or excessively complex control logic (PCIe). There are larger more powerful open source chips, but they are also more expensive, or just not available until the AI bubble bursts and manufacturing capacity becomes available.

It is a 40nm process, at the low end of the market, but has a lot of great functionality.

Lattice ECP5 feels just right. It supports a wide range of digital I/O. Multiple voltages, high speed gearing, higher speed Serdes, 3.2G by default which is enough for 2.5G Ethernet. There are multiple shipping boards one can use to get started. There is a very active Radiona ULX3S open source community supporthing this chip. The more I learn about the chip, the more I like it.

The ECP5 family supports 1080p (1920 * 1080) DVI out at 60 frames per second. ICE40 and GateMate cannot do that. ECP5 supports SDRAM as video frame buffers at the same 1080p @60FPS rate. This involveds DDR3 at 800 Transactions/s. 3.3 V is supported which makes it easy to interface to the Raspberry Pi ecosystem. In contrast, GateMate and Lattice's NX17/33/40 need level shifters to connect to RPI chips. The SerDes interfaces support MIPI-DSI, Embedded Display Port, multiGigabit Ethernet, PCIe, and more. ECP5 supports LVDS with 7:1 gearing, which would work well with the Sony Block Camera with 30 x physical zoom.

Inside the ECP5 there are 12K to 85K LUT-4s, 576Kbits to 3.7Mbits BRAMS, and 28 to 156 18 × 18 multipliers. The full details can be read in the ECP5 Datasheet.