Review of Ethernet SGMII (8B/10B SERDES) Concepts

Overview This article reviews various SGMII (& 1000BASE-SX) concepts that are integral to our Private Island ® project and its soft Verilog MAC layer. We provide oscilloscope screen shots below to help illustrate the concepts.

As shown in the block diagram below, Private Island utilizes a SERDES capable FPGA, such as the Intel Cyclone 10 GX on our company's Volitio™ board, to interface with SGMII Gigabit Ethernet PHYs and other SERDES-based peripherals.

Unlike a typical SoC, an FPGA is capable of asserting an external interrupt synchronous to specific packet transmit or receive events. The interrupt can also assert on specific octets / special codes within the Ethernet frame (i.e., end of packet). This interrupt flexibility is important for certain security functions and provides a reliable and predictable way to trigger our scope during debug of the SGMII / SERDES bus for both hardware and software debug.